An interframe deinterleaving circuit is employed as a means for dispersing a burst error in the PCM voice signal of the a high definition television broadcast. However, because there is a possibility of employing different interleaving lengths between a transmission system and a package system and therefore a necessity for their switching arises, an interframe deinterleave switching circuit is now under consideration.
For this reason, the description will be directed to an example of the foregoing conventional interframe deinterleave switching circuit with reference to the drawings.
FIG. 4 is a block diagram showing a conventional interframe deinterleave switching circuit and FIG. 5 shows an example of an interframe deinterleaving circuit. In FIG. 4, 1 denotes an interframe deinterleaving circuit. In FIG. 5, 6 to 10 denote shift registers, 11 denotes a selector, 12 denotes a counter, denotes an n-decoding circuit, 14 denotes an m-coding circuit, and 15 denotes a selector.
Hereinafter, the description will be directed to the operation of the interframe deinterleave switching circuit having the foregoing arrangement.
An input signal is passed through n ones of the shift registers 6 to 10, each of which corresponds to one-frame of 1350 clocks of a voice signal. These shift registers thus serve to supply the resulting signals 1.sub.0, 1.sub.1, 1.sub.2, 1.sub.3, . . . 1.sub.n-2, 1.sub.n-1, 1.sub.n including the input signal 1.sub.0.
A counter 12 starts to count at an initial value and sends out the output to an n-decode circuit 13. When the n-decode circuit 13 converts the output into n, a CLEAR signal f.sub.1 appears. When the m-decode circuit 14 converts the output into m (m&lt;n), a CLEAR signal f.sub.2 appears. Then, the selector 15 switches F.sub.1 to f.sub.2 in response to a switching signal from the external unit and sends out the output g to the counter 12 for clearing it.
When f.sub.1 is conveyed on the switching signal, the counter 12 repeats counts of 0 to n. And, the selector 11 serves to sequentially select one of the input signal 1.sub.0 and those outputs 1.sub.1, 1.sub.2, to 1.sub.n-1, 1.sub.n of the shift registers 6 to 10 in response to the output of the counter 12.
The foregoing arrangement, however, has a disadvantage in that it is necessary to pick up a switching signal for an interleave signal from the external unit.